(1) Field of the Invention
The present invention relates generally to a method of manufacturing a MOSFET with a recessed-gate, and more particularly, to a method of forming a MOSFET with a recessed-gate having a channel length beyond the photolithography limit.
(2) Description of the Related Art
Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. The ULSI circuits are generally composed of complementary metal oxide semiconductor field effect transistors (MOSFETs). Each MOSFET contains a gate electrode disposed between a drain region and a source region. In order to increase the device density and operating speed of the integrated circuits, the feature size of transistors within the circuits must be shrunk down. Particularly, in scaling down devices, a P-channel or an N-channel with shorter channel length is needed to enhance the operating speed.
Generally, photolithography process is a critical technique for shortening the channel length of a MOSFET. It is believed that the achievable minimum channel length depends on the photolithography limit of the lithographic tool, e.g. a stepper or a scanner.
In order to succeed at sub-0.1 xcexcm gate dimensions and below, a recessed-gate MOSFET with out-diffused source/drain extension was disclosed in U.S. Pat. No. 6,093,947. Referring first to FIG. 1A, according to this prior art, a semiconductor wafer 10 with a plurality of shallow trench isolation (STI) 12 is provided. A pad oxide layer 34 and a dielectric layer 36 are formed on the semiconductor wafer 10. Next, a hole 38 is formed in the structure extending into the semiconductor wafer 10. The hole 38 has sidewalls and a bottom wall. Thereafter, oxide spacer regions 22 are formed on the sidewall of the hole 38, wherein the oxide spacer regions 22 contain a dopant material which can out-diffuse when subjected to annealing.
Referring now to FIG. 1B, a gate oxide region 24 is formed on the bottom wall of the hole 38. After that, a conformal layer of polysilicon 40 is formed in the hole 38 and on the dielectric layer 36, and then a CMP process is performed to remove the polysilicon layer 40 outside the hole 38, as shown in FIG. 1B.
Referring now to FIG. 1C, the dielectric layer 36 is removed to expose the pad oxide layer 34 and outer walls of the oxide spacer regions 22. Source/drain regions 14/16 are formed in the semiconductor wafer 10 adjacent to the hole 38.
Finally, as shown in FIG. 1D, an annealing process is performed to cause out-diffusion of the dopant from the oxide spacer regions 22 to the semiconductor wafer 10 so as to form an extension 30 which wraps around the oxide spacer regions 22 and provides a connection to a channel region which is located beneath the gate oxide region. After that, nitride double spacers 19 are formed over the pad oxide layer 34. Finally, metal contacts, i.e. regions 32 and 26, are formed in the structure.
However, according to the prior art, the achievalble minimum channel length equals to the photolithography limit, when the photolithography process for forming the hole 38 is performed under the photolithography limit. In order to obtain shorter channel length for improving operating speed, it will be necessary to develop a new technology for forming a MOSEET.
Accordingly, it is a primary object of the present invention to provide a method of forming a MOSFET with a recessed-gate having a channel length beyond the photolithography limit.
It is another object of the present invention to provide a method of forming a MOSFET with a recessed-gate.
A method of forming a MOSFET having a recessed-gate with a channel length beyond the photolithography limit is disclosed in the present invention. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate, wherein the first dielectric layer and the second dielectric layer have selective etchability. For example, the first dielectric layer is composed of silicon dioxide and the second dielectric layer is composed of silicon nitride or silicon oxynitride. The second dielectric layer has a thickness between 1000 to 2000 Angstroms.
Next, a first opening is formed in the second dielectric layer. After forming first spacers on sidewalls of the first opening and removing the first dielectric layer within the first opening, a trench is formed in the semiconductor substrate by an anisotropic etching process. After forming second spacers with dopant source material on sidewalls of the trench, a gate dielectric layer is formed within the trench.
Thereafter, a conductive layer is formed to refill said trench. After removing the portion of the conductive layer outside the trench, a gate plug is then formed. After removing the second dielectric layer, source and drain regions are formed by an ion implantation process. After that, source/drain extensions are formed by an annealing process to out-diffuse the dopant material to the semiconductor substrate.
Finally, after forming third spacers on sidewalls of the first spacers, metal contacts for the source and drain regions and the gate plug are formed.